Multi-level, forming and filament free, bulk switching trilayer RRAM for neuromorphic computing at the edge

CMOS-RRAM integration holds great promise for low energy and high throughput neuromorphic computing. However, most RRAM technologies relying on filamentary switching suffer from variations and noise, leading to computational accuracy loss, increased energy consumption, and overhead by expensive program and verify schemes. We developed a filament-free, bulk switching RRAM technology to address these challenges. We systematically engineered a trilayer metal-oxide stack and investigated the switching characteristics of RRAM with varying thicknesses and oxygen vacancy distributions to achieve reliable bulk switching without any filament formation. We demonstrated bulk switching at megaohm regime with high current nonlinearity, up to 100 levels without compliance current. We developed a neuromorphic compute-in-memory platform and showcased edge computing by implementing a spiking neural network for an autonomous navigation/racing task. Our work addresses challenges posed by existing RRAM technologies and paves the way for neuromorphic computing at the edge under strict size, weight, and power constraints.

Through the Al 2 O 3 tunnel barrier, direct tunneling or FN tunneling can occur depending on the voltage applied and electric field across the Al 2 O 3 . 1,24][5] The equations for all these mechanisms are as follows.:

Supplementary note 2
To quantitatively analyze the device non-linearity, we investigated non-linearity of the trilayer bulk RRAM devices using the following equations. 6 We demonstrated weight updates using both identical and incremental pulse schemes.When we adopt the identical pulse scheme, the non-linearity values of +3.68 and -4.34 (Fig. S3a) during the potentiation and depression were achieved.The non-linearity could be improved to -1.24 and -4.21 (Fig. S3b) for the potentiation and depression process by using the incremental pulse scheme.We expect that the non-linearity could be further improved by optimizing the pulse amplitude and width for potentiation and depression in the incremental scheme.Furthermore, there are algorithm-device co-design approaches that can be adopted to compensate system-level effects of switching nonlinearity.For instance, to mitigate the non-linearity effect on accuracy drop in online learning and classification tasks, we previously developed the adaptive quantization method, which maps weights onto the device conductances based on the distribution and relative-importance of the weights. 7Various other nonuniform quantization methods have also been adopted by the broader neural networks community to improve efficiency of neural networks. 7he current conduction occurs through direct tunneling, FN tunneling, and SCLC models.Based on these models, we simulated the current density under the electric field with various tunneling barrier (Al 2 O 3 ) thickness layers.We varied tunneling barrier thickness from 20 Å to 40 Å, and the current density of them were plotted in Fig. S8a.As the current density in the direct tunneling exponentially decays with the oxide thickness, we expect the current density to be decreased by around 3 orders of magnitude per 1 nm Al 2 O 3 thickness.These simulation results suggest that to set the device resistance to in ~MΩ regime, the Al 2 O 3 tunneling barrier thickness should be chosen ~30Å.So, we have decided 30Å of Al 2 O 3 tunneling barrier to make our devices in ~MΩ regime.We plotted the current density of an experimentally measured RRAM device with 30Å tunneling barrier thickness and 5μm diameter (shown with open circle in Fig. S8a) showing 1MΩ resistance at 100 mV read voltage, showing great consistency with predictions based on the tunneling current calculations.Our methodology suggests that there is more room to modulate the barrier thickness depending on the target resistance and the device size.
Once the tunnel barrier thickness is fixed, we systematically optimized the thickness of SCLC conduction layer made of TiO x .Thinner TiO x will result in higher electric field across the SCLC layer for the same applied voltage and hence will increase the chances clustering of oxygen vacancies through drift to form filaments.To observe this, we chose two different TiO x thicknesses (6.5 nm for S3 and 40 nm for S4) leading to a difference in the applied electric field across the SCLC layer.We fitted the J-V data of both S3 and S4 using tunneling and SCLC conduction models, and we extracted the electric field applied across the TiO x switching layer shown in Fig. S8b below.Since S3 has a thinner sputtered layer than S4, it causes a higher electric field across the TiO x switching layer.The electroforming step in filamentary RRAM devices corresponds to the controlled soft-breakdown process in a thin insulator film. 8,9Therefore, the thin oxide film or high electric field are known to induce facile filament formation behavior in the RRAM devices.Due to high electric field in S3, it causes filament forming under a high voltage regime (|V| > 1V) as seen in Fig. 1g in the manuscript because the V O filaments protrude the whole switching layer.This filamentary switching mechanism is the same as the ALD bilayer filamentary RRAM devices (S1 and S2).
In a lower voltage regime (|V| < 1V) where electric filed is not large enough to drift and cluster V O , it shows bulk switching behavior through modulation of V O distribution across the switching layer.In S4, however, we successfully suppressed the filament formation by reducing the electric field with a thick and amorphous TiO x layer so that we could achieve stable bulk switching behavior.
The difference between S3 and S4 is the applied electric field across the sputtered TiO x layer.We fitted the J-V data of both S3 and S4 using tunneling and SCLC conduction models, and we extracted the electric field applied across the TiO x switching layer (Fig. S8b).Since S3 has a thinner sputtered layer than S4, it causes a higher electric field across the TiO x switching layer.The electroforming step in filamentary RRAM devices corresponds to the controlled soft-breakdown process in a thin insulator film.Therefore, the thin oxide film or high electric field are known to induce facile filament formation behavior in the RRAM devices.Due to high electric field in S3, it causes filament forming under a high voltage regime (|V| > 1V) because the V O filaments protrude the whole switching layer.This filament switching mechanism is the same as the ALD bilayer filamentary RRAM devices (S1 and S2).In a lower voltage regime (|V| < 1V), it shows bulk switching behavior due to a change in defect distribution across the switching layer.In S4, however, we successfully suppressed the filament formation with a thick and amorphous TiO x layer so that we could achieve stable bulk switching behavior.
Al 2 O 3 /TiO 2 materials not only address the limitations of the mature filament RRAM technologies but are also compatible with integration at the CMOS BEOL to enable a high-density 3D compute-in-memory platform for neuromorphic applications.Based on Table S2, the key figures of merit of our bulk RRAM technology RRAM technology can be summarized as follows; forming-free operation, CMOS BEOL compatibility, high R on and R off that enables reliable read and write in large scale crossbar arrays and low energy operation, low switching voltages, high number of conductance states, endurance comparable to RRAM technologies, and much lower total read energy.We have estimated the stoichiometry of the sputtered TiO x and ALD TiO 2 film in Table S1.We expect the stoichiometry of the sputtered TiO x layer to be around TiO 1.85 based on our experimentally measure conductivity and O 2 /Ar ratio during the sputtering process 15,16 .Due to the intentionally induced V O defects, SCLC conduction occurs through the layer in comparatively higher electric field than where the ohmic conduction occurs in the TiO x layer.Table S3.Sheet resistance uniformity of sputtered TiO x layer across the wafer.
To investigate uniformity of the films, we deposited 50-nm thick of sputtered TiO x layer on a 4inch SiO 2 /Si wafer and measured the sheet resistance across the wafer.We confirmed highly uniform sheet resistance and device switching behavior across the whole wafer which can address the reproducibility and variability issues in filament RRAM devices.
=   +   (S5)  = ,  ∝ exp(+1  2+1 ,  =   / (S7)Where e is the electron charge, s is the Al 2 O 3 layer thickness, h is the Planck constant,  * is electron effective mass,  1 and  2 are barrier heights of Al 2 O 3 layer from metal and TiO x sides respectively, Φ is average barrier height of Al 2 O 3 layer, n is the free electron density,  is the mobility of electron, N c is the effective density of state in the conduction band,   is the dielectric constant of TiO x ,  0 is the permittivity of vacuum, N t is the trap density, d is the TiO x layer thickness, T c is the characteristic temperature, m is   /.T c is the characteristic temperature defining the slope of the exponential trap distribution over bandgap energy.3

Figure S2 .
Figure S2.Experimentally measured I-V and fitted curve with different temperature from 300K to 350K.a. Whole range, log Jlog V curves.b.Magnified image of log(J/V 2 ) vs. 1/V curves from 0V to 0.1V.c.Magnified image of log(J/V 2 ) vs. 1/V curves from 0.25V to 1V.Experimentally measured data (dotted

Figure S3 .
Figure S3.Normalized conductance vs. Normalized pulse using a. identical and b. incremental pulse

Figure S4. a .
Figure S4.a. Endurance and b. read noise during the endurance tests up to 2×10 5 pulses.c. read disturb

Figure S5. a .
Figure S5.a. Read margin for different R OFF and array size simulated for the worst-case (selected cell is

Figure S6 .
Figure S6.Average energy consumption and its variance during navigation of all 15 racetracks by using

Figure S7 .
Figure S7.Total energy consumption during navigation of three representative racetracks by using different

Figure S8. a .
Figure S8.a. Current density versus applied voltage across the RRAM switching layer.The Al 2 O 3 thickness

Table S1 .
Stoichiometry estimation by conductivity measurement and XPS analysis.